Welcome!

Welcome to our website dedicated to improving your analog verification capabilities or to get you started quickly on analog verification. This page defines analog verification, specification-driven analog verification, presents the value of our solutions, and discusses how we provide our solutions. Our previous website is still at link.

The steps above show the process to getting started. We begin by presenting the value that we bring. We then ask that you register to learn the details on our offerings. This includes more on analog verification, and we will discuss specification-driven design in more detail. We present common scenarios that we have observed at companies and design teams, why these scenarios are problematic, and what can be done. We present success stories and technical details. And we describe our solutions and offerings. Much of what is found in the details is exclusive to this website.

The content on this website is a collection of what we typically present to customers prior to working with us including all that is necessary to do an evaluation of our solutions. Finally, although we present a set of steps for getting started, we are flexible, and we would enjoy talking to you. If at anytime you have questions and would like to have a discussion, please contact us at sales@designers-guide.com. Thank you for visiting!

– Henry Chang and Ken Kundert, Co-founders of Designer's Guide

What is Analog Verification?

We use the term, analog verification, to mean any verification that touches the analog. This includes mixed-signal verification, digital/mixed-signal verification (DMS), analog/mixed-signal verification (AMS), chip-level verification, analog block-level verification, and analog system performance level verification. Move the mouse over the blocks in the chip diagram to see more on each step.
Catches simple and complex errors:
  • Inverted signals
  • Corrupt logic
  • Signal conflicts
  • Misconnected buses
  • Missing level shifters
  • Incorrect dependency loops
  • Errors due to human communication errors
Functional errors are often catastrophic!

Analog verification must find all bugs related to the analog at the chip-level and block-level. We support all analog verification efforts including mixed-signal, AMS, DMS, and performance verification!

We find both simple and complex errors, but often the simple ones are catastrophic. Our experience has been that approximately 50% of the analog related bugs are found in the analog itself, while 50% are found everywhere else. We define:

  • Mixed-signal verification broadly typically referring to verifying digital (RTL) and analog together. The term may refer specifically to chip-level verification of a mixed-signal part.
  • Analog/mixed-signal (AMS) verification as verifying the analog system in the presence of digital. This effort is usually driven by the analog team starting from the analog block schematics. The models developed tend to be more detailed and more electrical in nature and are often written in Verilog-AMS. The verification goals include verifying the analog top-level netlist, communication of RTL with analog, looking for missing level shifters, and may include some critical system-level performance analysis.
  • Digital/mixed-signal (DMS) verification as verifying the digital system in the presence of analog. This effort is usually driven by the digital verification team and their starting point is the chip-level simulation. The models developed tend to be less detailed and more functional in nature and are often written in SystemVerilog. They tend to abstract analog signals as real numbers, but increasingly they are employing pseudo-electrical ports in an event-driven simulator taking advantage of SystemVerilog nettypes. The verification goals start with the digital verification goals and add analog connectivity, followed by analog functionality to the digital. A typical starting point is to verify the power-up sequence for a chip.
On large chips, there are often two teams, one for digital/mixed-signal verification, and another for analog/mixed-signal verification. The teams may each have their own models for the analog and are often working at two different abstraction levels. For medium sized mixed-signal chips, there tends to be one verification team with one set of the models for the analog.

We support all of these efforts!

What is Specification-Driven Analog Verification?

In specification-driven analog verification, executable specifications are created for each of the analog blocks. Two flows are shown in the diagram below – the analog design flow and a chip-level verification flow. In the analog design flow, block-level analog design typically starts with specifications for the blocks. Often the specifications are informal and used only to initiate the design. The schematics often serve as the "golden" to describe what is in the design. By formalizing the specifications and thus making them executable, they can be used to automatically generate the model and testbench, which is used to confirm that the behavior of the model and the schematic are equivalent. In a bottom-up flow, the executable specifications are created after the schematics are created. In a specification-driven design (top-down) flow, the executable specifications are created first, and the schematics would be designed based on the specifications. In the chip-level verification flow, the RTL, models, and top-level schematics are verified together. In larger chips, this flow might take place at a subsystem level. Move the mouse over the blocks in the flow diagram to see more.
analog design flow
chip-level
verification flow
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Specification-Driven Analog Verification
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Specification-Driven Analog Verification and Design
hover to show how specification-
driven verification leads to top-down design

Models form the linchpin of the analog and digital flows. Executable specifications ensure that this linchpin is created efficiently, and in specification-driven design, early in the design process. Executable specifications enable specification-driven design. With a bottom-up flow, the first time through the analog verification process, executable specifications are created. In the next design, the specifications can be used to start the next design process. Executable specifications facilitate moving to top-down design if desired.

With executable specifications, analog verification and top-down design go hand-in-hand, though neither is necessary for the other. Traditionally, people use the term top-down design to mean that designers start with models of their blocks before designing schematics. This has many advantages. They include being able to simulate the analog system early, having the digital co-designed and co-verified with the analog early, and being able to define interfaces early in the design process. However, the biggest shortcoming of top-down design, and why few use this approach is that the process of writing models is non-trivial. Most analog designers lack the expertise, have no interest in writing models, and perhaps most importantly, practically speaking analog designers have mostly been fine designing their blocks and meeting performance specifications without models. Since model writing is problematic, a solution that does not involve model writing is required. We focus on using specifications which are reminiscent of the specifications designers and design-leads already create in either a spreadsheet or a document, except that we formalize them to make them executable. The specifications are human readable, thus making them designer friendly, unlike models. If these executable specifications are created before schematics are designed, we refer to this as specification-driven design.

From the executable specification, a model and testbench is generated. The testbench is self checking, and verifies that the model and the schematic are equivalent. If you are employing a top-down approach, then specifications are entered at the start of the design, and the model generated can be used for system development. Then when the schematics are ready, the testbench is run to verify that the model and schematic are equivalent. If top-down design is not used, then specifications are entered typically by looking the schematics. Because of the succinct nature of the specifications, models and testbenches can be created 100x faster.

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Evolving Analog Verification Concerns

Since 2005 when we started Designer's Guide, the concerns in analog verification have shifted from where to find people to write models to how to make analog verification maintainable and scalable. Below is a diagram illustrating the evolution of analog verification from the point-of-view of what was of the highest concern at a particular moment in time for the companies truly embracing and getting the maximum value from analog verification. Mouse over the diagram below for details.
2009
2012
2015
Analog verification is changing quickly. Every three years, there seems to be a fundamental change in focus layering on top of previous concerns. The change is very much fueled by the rapid changes in analog and mixed-signal design. Analog verification groups cannot rest and must continue to evolve their methodologies to meet current challenges. Designer's Guide is focused on providing solutions that meet all of the needs from 2005 to today, 2018. We take pride in being able to quickly respond to our customer's requirements. That is why our solutions meet the needs of today.

It is often difficult to see beyond one's primary concern. We hope that this roadmap chart helps. For example, if your primary concern is still on writing models, know that once you get past this hurdle, there will be several more significant hurdles to getting the maximum value from analog verification.

Value of Our Solutions

We bring a complete solution. Analog verification touches many groups working on mixed-signal chips. We bring value, in a timely manner, to all of these groups. Each of the groups have a stake in the success of analog verification, but for slightly different reasons given their responsibilities. Move your mouse over the different groups below to see the value that we bring.



At a higher-level:
  • Better ensure having first working silicon – get to revenue faster, greatly reduces risk of losing socket
    • Discover bugs that would have otherwise been missed (analog verification) – the verification team is looking for bugs in your entire design
    • Discover bugs earlier in the design cycle (specification-driven design)
  • Design more complex mixed-signal chips – better performing analog that requires RTL; analog chips with complex RTL, micro-controllers, and micro-processors; chips where safety and redundancy are a concern, e.g. ISO 26262
  • Leverage and develop analog verification IP. Every verification effort that follows the first will leverage and build on previous IP for even more value
  • Have us do the work, and have your experts focus on what you hired them for!
Beyond specification-driven analog verification, specification-driven design is a next evolutionary step in analog design. With an executable specification the digital design and verification teams can have early access to the analog block models so that the digital and analog can co-simulate and co-verify.

Benefits for the analog designer

  • Without verification, complexity leads to errors. Without an effective analog verification process the design must be kept small and simple with limited connections to the digital portion of the design to avoid mistakes. This places limits on the kinds of designs that can be attempted, and often prevents the use of digitally-assisted analog circuit techniques. An effective analog verification methodology eliminates these constrains, allowing designers to design more complex and often more lucrative circuits using the latest techniques.
Benefits for the analog designer, analog design lead, and system designer
  • By going specification-driven, the analog design lead puts together an early version of the top-level schematics and has a better sense of the operation of the analog system earlier in the design process. With executable specifications, designers easily understand what is being modeled and tested without having to read and understand model or testbench code. They easily critique the contents of the model and even make improvements, and use the specification as a starting point for understanding the design requirements.
  • We can help with simulation for performance, especially at a system or a macroscopic level. Once functional models have been put in place, analog impairments can be added to the models, such as timing delays. Process, voltage, and temperature corners can also be added to give an idea of the performance of the analog system in the presence of the impairments. There is an expense with adding performance to models. Give a particular architecture, we focus on adding performance to the key blocks in the system that have the largest impact on performance. Finally, depending on what is being modeled, rather than using classic voltage and current modeling, we use other electrical quantities for better accuracy and efficiency. This includes baseband equivalent modeling, but there are other domains as well for commonly used circuits.
Benefits for the digital design and verification team
  • For the digital design and verification team – simply put, our goal is to make your challenge with the analog go away. We focus on getting to the digital design and verification team high quality (efficient, robust, up-to-date and maintainable) models of the analog blocks early in the design process. The models are designed to fit seamlessly into your digital verification flow, and probably most importantly, delivered in a way where you do not need to worry. Further, the analog block models will be updated as the analog design changes. They will be checked-in in accordance to your revision control and tagging system, and when the analog schematics are done, the models will be verified to be equivalent to the schematics. The models can be in a language and in a style of your choosing. Many are using SystemVerilog either with a real or pseudo-electrical nettype transport mechanism for the analog signals. The models will adhere to your digital standards for the digital signals, and the models can be set up to fit into your UVM or UVM/mixed-signal flow.
  • Also, it is fairly typical that a company has no true owner of the entire verification approach, and often no one with a clear vision across all domains. We can help explain all to all groups of the puzzles pieces and what is necessary for an entire solution.
Benefits for the methodology and CAD people
  • For the methodology and CAD people – It is typically all about consistency. Why is that? They see how much time is wasted across the company in using and maintaining models. A small gotcha in how a single model was written out of the possibly 100 models in a chip-level simulation can easily grind work to a halt for two or three days until the problem and a solution is found. And when that solution is found, there's typically no way to deploy it so that it does not happen again. Nothing is more frustrating than re-discovering the same issue over and over each with a cost of two or three days at the most critical time during a design, when the chip is being pulled together and full chip-level simulations are being run. So, the methodology and CAD people see a critical need for the use of consistent best practices in verification. With each new discovery if that discovery can be codified, then it is one less thing to worry about in the hundreds of things that can go wrong during a chip-level simulation. They recognize that their company may have experts who might know 80% to 90% of these best practices, but the methodology and CAD people recognize that there are only a few experts (if any) at a company, not enough to develop the models needed and not enough to provide support to others writing models. Further, the experts forget also, and do not always incorporate everything they know into every model. They can also end up rediscovering the wheel.
  • Our solutions incorporate accumulated knowledge in the industry and deploy them consistently. And where we have codified best practice in our model generator, those are automatically deployed in current, and legacy models when driven from an executable specification, meaning that as new best practices are discovered, most of the time no additional effort is required to deploy that newly found best practice in all legacy models. We spend our time debugging issues and developing solutions and adding to our set of best practices. Our customers benefit from that. There are simply too many things to remember. One of the reasons why we developed the executable specification initially was so that we at Designer's Guide wouldn't need to remember every little detail when writing models. Now, with our solution, no one needs to remember those details.
  • The methodology people also worry about maintainability. A designer can read an executable specification, but they typically cannot understand someone else's model code, and a few months later, they often cannot understand their own code. The executable specification addresses this issue as well.
Benefits for the VP of engineering and design director
  • For the VP of engineering and design director – they want their designers focused on their core competency, and not chasing down endless issues with verification. They also recognize that with the design cycles as short as they are, getting all chips out with first functional silicon is all about getting the myriad of details right. Minimizing failure is all about execution and following process. They also do not want to compete in something other than their core competency. Our verification solutions let the design teams focus on their core competency. Depending on your competition, we can either give a company a leg up, or help a company catch up. The companies that are successful have an effective and comprehensive analog verification solution and some have moved to specification-driven design.
  • A common complaint from the VP of engineering or the design director in a company that conducts analog verification is that verification takes too long, and there is too much of it. They willingly invest in verification, but are now taking a step back and seeing that verification is now taking a significant amount of resource. Upon seeing this, however, they are unwilling to scale back because the risk of not having first time silicon is worse than the expense for verification. From a technical perspective, usually this is the result of simulations taking too long taxing the digital verification team, and the analog team being taxed too heavily for needing to create models while also running their own analog system simulations. Regardless of the exact details, our solution tackles this issue from many perspectives, and basically, for the same amount of coverage, we can reduce the amount of time verification takes, and we can reduce the cost.
For more details, please register. For more general information, please read about analog verification here.

Designer's Guide Complete Solutions

Answer the questions in the diagram below to see the solution that we would recommend (mouse over boxes for details).
We handle your verification


Our solutions are comprised from three dimensions – technical expertise and know-how, production ready, and adaptable.
Technical Expertise and Know-How
  • Deep simulation and modeling know-how
  • Domain specific analog verification IP and know-how
  • Over a decade of experience engaged in analog verification
  • Successfully trained many teams including our own services team on analog verification and specification-driven design
  • Repeatedly reduce chip-level simulation times even when the chip is simulating with all models from 24 hours to less than an hour.
Production Ready
  • Automatable and Executable
  • Systematic
  • Scalable and Repeatable
  • Accurate, efficient and robust
  • Tested
Adaptable to Specifics
  • Our solutions have been adapted to work optimally in different domains. For example, in automotive, there are safety and redundancy requirements (ISO 26262) which poses verification challenges. Consumer, IoT, and industrial have different requirements also.
  • Our solutions work with almost all circuit types. Different circuit types often have some unique characteristics that can pose challenges. For example, switching regulators have inductors and a power transistor at a high-level in a hierarchy. Switched capacitor circuits are particularly suited for certain efficiency optimizations.
  • Your end customer may have verification requirements as well. We adjust our solution to fit those requirements.
  • We can go beyond analog verification, and can deliver you an entire verification solution including the digital verification.

We mix n' match our offerings and deployment them in a manner that best fits your needs.
Offerings
  • MiM – our executable specification entry, model and testbench generation platform enables specification-driven analog verification
  • Classes – develop and improve your verification team's know-how
  • Consulting – get high level guidance to get you going in the right direction and avoid pitfalls
  • Contract services – supplement or take a portion of what you do
  • Subscription services – full service offering where we take the burden of some or all of your verification needs
Deployment Options
  • We provide do it yourself solutions
  • We provide do it yourself with some help solutions
  • We'll do the verification for you and plug seamlessly into your flow

For us to be able to help, we just need to know how you would like us to help. This website will help determine your situation to figure out what solution will work best.

We meet you where you are. We work with customers at differing stages of analog verification and specification-driven design. Some are brand new to the methodologies. Some are experts. And some just cannot be bothered doing any of this themselves but still want it done. Included in the details is also a discussion on how we can mix n' match our offerings to fit your needs. You might find yourself in a similar situation as described in one of the many scenarios that we present. Along with the scenarios are root causes and what can be done. If after going through the details, you believe that we can help, we ask you to tell us a bit more about your situation so that we can better find a solution that is a good fit. Then we will ask that we jointly sign a non-disclosure agreement (yours or ours). Then we can continue in even more detail including allowing you to evaluate our solutions before making a purchase.

We understand that there is a difference between knowing that there is a need, and knowing how to invest time and money to address the need. Also, for many of you, you have probably already begun to address the need, but you may feel that what you currently have is not adequate and are wondering if there are ways to improve. Is there a better solution? Will implementing that solution be cost effective?

We can help you answer those questions.

Supporting Experts and Non-Experts

We are committed to supporting experts and non-experts. For experts, many of you have already implemented custom capability similar to the features that we provide. Our goal is for you to have the best analog verification solution possible in as short of a time as possible. Throughout the MiM platform we have hooks for customization. If you already have something that works, that's great. Let's have a discussion to see how we can provide complementary technology to augment what you do. Because we are all about scalability, we may even be able to help with scaling what you have. Finally, we know that some of you enjoy writing code or want to have the power of writing your own code. We understand that, because we are experts as well. The capability of incorporating your own custom code into our system has been a feature from our product's inception.

If you are new to analog verification, through our subscription, we provide everything that you need, including classes to help you be successful with analog verification immediately. And we are happy to work with you, however, you would like. We can work on a more horizontal basis where we focus on bringing your entire team up-to-speed, or we can focus more on a chip-basis where we focus on doing the analog verification work for a particular chip. How we provide our solutions very much depends on your goals and where you would like your analog verification to be in the next year and beyond.

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